1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device having at least one component-forming region in a semiconductor layer on an insulator contiguous to a substrate.
2. Description of the Related Art
JP-A 9-97886 discloses a semiconductor device with a high power diode in a semiconductor layer on an insulator film contiguous to a conductive substrate. FIGS. 8 and 9 are simplified illustrations of FIGS. 14 and 15 of the JP-A 9-97886, respectively, and they are used in explaining the known semiconductor device.
Referring to FIG. 8, the reference numeral 1 designates a substrate for supporting a semiconductor. An N-type conductive semiconductor layer 2 is on an insulator film 3 that is contiguous to the substrate 1. At least one of two silicon plates is oxidized at one side and bonded to each other with the oxidized side in by thermal oxidation. One of the silicon layers is polished to provide a semiconductor layer with a predetermined thickness.
Two highly doped zones, namely a N+ type conductive zone 4 and a P+ type conductive zone 5, are diffused into the N- type semiconductor layer 2. The diffusion boundary of the P+ type conductive zone 5 extends down to the insulator film 3. These zones 4 and 5 form the cathode and anode, respectively, of a diode. The cathode 4 is provided with a cathode contact 6. The anode 5 is provided with an anode contact 7. The substrate 1 is provided with a substrate contact 8. Between the cathode contact 6 and the anode contact 7, an insulator file 11 extends laterally so far across the surface of the semiconductor layer 2. The semiconductor layer 2 is electrically insulated and separated into a plurality of component forming regions. An insulator zone 9 extends down to the insulator film 3 and is contiguous to the P+ type conductive zone 5 to electrically insulate a component-forming region in which the diode is formed.
Referring to FIG. 9, the substrate 1 and the anode 5 are at earth potential and the cathode 4 is at high potential. Under this condition, a depletion layer (DP) A extends laterally from the P-N junction between the P+ type conductive zone 5 and the N- type conductive semiconductor 2. A depletion layer (DP) B extends vertically upwards from the interface between the semiconductor layer 2 and the insulator film 3 because the substrate 1 serves as a field plate via the insulator film 3. The depletion layer B facilitates further lateral extension of the depletion layer A. This brings about a considerable reduction in strength of electric field at the P-N junction.
According to this known semiconductor device, a substrate contact 8 extends across the under side of the substrate 1 to keep same at predetermined potential. This involves potential problems as follows:
(1) In light of current movement to a single chip implementation of semiconductor components of a system, a ball grid array (BGA) and a chip size package (CSP) technologies are widely employed as an integrated circuit (IC) package. In these technologies, a chip is connected facedown with a wiring layer by means of bumps formed on the surface of the chip, so that connection of the under side surface of the chip with the wiring layer is difficult to make. PA1 (2) Using insulating paste is the common measure in connecting a chip with a wiring layer by wire bonding and die bonding techniques because it brings down cost of the die bonding. This measure cannot be used in connecting the under side of the chip with the wiring layer. PA1 (3) With the substrate contact at earth potential, the substrate is kept at the earth potential over the entire surface. Thus, a reduction in strength of electric field is not expected in each of all semiconductor components that are distributed over the entire surface of the substrate, if they include N type conductive components and P type conductive components. PA1 a substrate; PA1 an insulator contiguous to said substrate; PA1 a semiconductor layer on said insulator; PA1 a component forming region in said semiconductor layer; PA1 a substrate access region extending from a surface of said semiconductor layer down toward said substrate and electrically insulated from said component forming region; and PA1 a substrate contact on the surface of said semiconductor layer within said substrate access region for the control of a surface potential of said substrate. PA1 a substrate divided into a first region and a second region; PA1 an insulator contiguous to said substrate; PA1 a semiconductor layer on said insulator; PA1 a first component forming region in said semiconductor layer and over said first region of said substrate; PA1 a second component forming region in said semiconductor layer and over said second region of said substrate, PA1 a first substrate access region extending from a surface of said semiconductor layer down toward said first region of said substrate and electrically insulated from said first and second component forming regions; PA1 a second substrate access region extending from the surface of said semiconductor layer down toward said second region of said substrate and electrically insulated from said first and second component forming regions, PA1 a first substrate contact on the surface of said semiconductor layer within said first substrate access region for the control of a surface potential of said first region of said substrate; and PA1 a second substrate contact on the surface of said semiconductor layer within said second substrate access region for the control of a surface potential of said second region of said substrate.
The known semiconductor device is fairly well developed in making a reduction in strength of electric field at the P-N Junction. However, a need remains for further development of such semiconductor devices, in light of current movement to a chip-scala packaging.
An object of the present invention is to modify the semiconductor device of the above kind such that it can be implemented as a chip that may be employed by chip-scale packaging technology.